1. Field of the Invention
The invention relates generally to semiconductor memories and more particularly to a method of forming memory post structures for high density dynamic random access memories (DRAMs).
2. Description of the Related Art
Over the years, as the dynamic random access memory devices have been scaled down in size, the minimum amount of stored charge needed to maintain reliable memory operation has remained the same. This constant charge-storage value has to be maintained for future DRAM generations as well even as the cell sizes shrink even further.
As is well known in the art, the storage capacity of capacitors in memory cells can be increased by making the capacitor dielectric thinner, by using an insulator with a larger dielectric constant, or by increasing the area of the capacitor. The first two options are not currently viable, since capacitor dielectrics thinner than those now being used in DRAM cells (10 nanometers) will suffer leakage due to Fowler-Nordheim tunneling, and dielectrics with significantly larger dielectric constant than of SiO.sub.2 have not yet been accepted for DRAM-cell application. (S. Wolf, "Silicon Processing for the VLSI Era," vol. 2, p.598, Lattice Press, Sunset Beach, Calif., 1990). The third option of increasing the capacitor area can be effective and has been exploited in certain different ways. One way is to form three-dimensional structures in place of planar capacitors. In this approach, the storage capacitor is formed in a trench etched in a semiconductor substrate. The silicon-area reduction of a trench capacitor compared to a planar capacitor can be a factor of eighteen or more, for example. In another approach, the storage capacitor of a cell can be formed, or stacked, on top of its access transistor, thereby shrinking the cell size without a loss of its storage capacity. In still another approach, a three-dimensional effect can be realized by forming a finned structure with leaves extending from the same capacitor trunk. Many variations of such three-dimensional capacitors are reported in prior art.
General usage of trench structures are well known in isolation technology where they are used to isolate devices in integrated circuits. There are differences in these structures, however, when they are used for DRAM capacitors, in particular. As stated earlier, storage capacity is inversely proportional to the dielectric thickness, and therefore, in the case of a trench capacitor, the dielectric film on the walls of the trench must be much thinner than on the walls of an isolation trench. Also, since polysilicon is usually used as the filler material in the trench, and since in the case of a trench capacitor this material also serves as one plate of the capacitor, it must consist of highly doped polysilicon. Usually the semiconductor on the other side of the thin dielectric serves as the other capacitor plate. The role of the polysilicon inside the trench as the storage electrode or plate electrode will vary depending upon the particular design used.
Similar considerations as in trench-capacitors apply when three-dimensional capacitors such as pillars or posts are formed above the access transistors on a semiconductor substrate. In prior art, some of these structures are referred to as stacked capacitors (STCs). (See Wolf cited above, p. 609). As usual, the properties of the dielectric, and the area of the capacitor play a significant role in determining the storage capacity. Thus, for STC cells to be made feasible for high-density DRAMs of 1 Mega-bit and made feasible for high-density DRAMs of 1 Mega-bit and beyond, an insulator with a larger dielectric constant than that of SiO.sub.2 must be made available, or novel structures must be developed. In the absence of the former presently, several novel STC cells have been reported in the literature. In one such cell, a three-dimensional STC structure above the substrate is extended downward by trenching into the substrate. Both the stack as well the trench extension are filled with polysilicon. In another approach, the wing-like storage electrode of one memory cell laterally overlaps a similar storage electrode of the neighboring cell with insulating material therebetween. Both of these structures are reported to be possible candidates for making 64 M-bit DRAMs possible, according to S. Wolf cited above. It will be seen in the present invention that still another post structure readily lends itself to the manufacture of very high-density DRAMs. Furthermore, it will be disclosed later that the forming of such a capacitor node in the form of a post eliminates the need for a mask for opening contact holes over the active regions on the substrate.
The said posts of this invention can also be utilized very effectively in the planarization process that is required subsequent to the forming of features on a substrate.
Planarization of integrated circuit devices is necessary and desirable to facilitate masking and etching operations. A planarized surface provides a constant depth of focus across the surface of the substrate for exposing patterns in a photolithography emulsion. Planarization becomes more difficult when the pattern of the features vary from location to location on the substrate, and especially when the aspect ratio (defined as the height of a feature divided by the distance to the closest feature) is greater than about 1.6 (U.S. Pat. No. 5,312,512). Known methods for planarizing sub-micron device geometries include multiple silicon oxide depositions with insitu etches to fill the spaces in between the features and then performing chemical mechanical polishing (CMP) which is well known in the art. However, as described in U.S. Pat. No. 5,312,512, this method suffers from the disadvantages of high expense, low throughput, process complexity and high defect density. In the present invention, by a judicious use of stand-alone pillars of the same shape and form as the posts used as capacitor nodes, the underlying pattern is made more uniform, and hence more amenable to CMP.
Post-like structures are also used in U.S. Pat. No. 5,094,972, however, by first forming a stop layer upon the surface of the substrate. Said stop layer is used to signal the end of polishing at a particular level in the multilevel structure. This step is avoided in the present invention. Since the various levels are interconnected through via holes therebetween, U.S. Pat. No. 4,582,563 proposes improving the reliability of such connections by forming via holes in two steps instead of forming the whole length of deep via holes through relatively thick insulating layers. The problem of forming interconnections through thick insulating layers is also addressed by U.S. Pat. No. 4,592,802. In order to prevent the rupture at the level of the contact opening win the insulating layer between the interconnection layer and the substrate, the contact openings are first filled with polycrystalline silicon and deposited by chemical decomposition in gas phase, whereupon aluminum is deposited by vacuum evaporation.
While the techniques described above may be employed in prior art, the novel post structures of the present invention provide additional structural integrity in general, and improved functionality, in particular, through increased capacitive characteristics.